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| KESRX01 290 - 460MHz ASK Receiver Advance Information DS3968 5.0 March1998 The KESRX01 is a single chip ASK (Amplitude Shift Key) Receiver IC. It is designed to operate in a variety of low power radio applications including keyless entry, general domestic and industrial remote control, RF tagging and local paging systems. This single conversion super-heterodyne receiver offers an exceptionally high level of integration and performance. The unique architecture enables data rates up to 50Kbits/sec to be supported. All low power radio regulations, including ETSI-ETS 300 220, and FCC, part 15, can easily be met. Local oscillator generation is performed by an on-chip PLL which uses an external crystal reference oscillator (4.5 to 7.2MHz). All popular radio frequencies (315MHz, 433.92MHz, etc) can then be supported by simply choosing the appropriate crystal frequency. Particular emphasis has been placed on low current consumption, with pulsed ON/OFF operation allowing <1mA average current consumption to be achieved. The on-chip VCO and IF significantly minimise the external components needed thus reducing any re-radiation effects. IFDC1 IFDC2 IF2 IF1 VCC MIXIP RFOP VEERF RFIN DSN DATAOP PEAK 1 2 3 24 23 22 21 20 19 18 17 16 15 14 13 XTAL2 XTAL1 DF2 DF1 DF0 LF NC NC VCO2 VCO1 PD VEE1 5 6 7 8 9 10 11 12 KESRX01 4 QP24 QPA24 Fig. 1 Pin connections - top view FEATURES s Very low supply current (2.30mA typical) s Low external part count s -105dBm sensitivity (typical 315MHz) s Integrated VCO and IF Filters. ORDERING INFORMATION KESRX01/IG/QP1T (Tape and Reel) KESRX01/IG/QP1S (Tubes) DF2 DF1 DF0 ABSOLUTE MAXIMUM RATINGS All voltages relative to V EE (0V) Junction temperature, Tj Storage temperature, Tstg Supply voltage, V CC max Voltage on any pin, Vshort -55 to +150C -55 to +150C V CC -0.5 to +8.0 V -0.5 to +8.0V IF DC1 IF DC2 IF 2 IF 1 MIXIP RFOP PEAK DETECTOR PEAK DATA FILTER + DATA SLICER - DSN VCC VEE1 PD XTAL OSCILLATOR RSSI O/P LOG AMP IF FILTER 600KHz DATOP MIXER DIV 64 PHASE FREQUENCY DETECTOR VCO RFIN LNA VEERF XTAL 1 XTAL 2 LF VCO 1 VCO 2 Fig. 2. Block diagram KESRX01 ELECTRICAL CHARACTERISTICS D.C. Tamb = -40 to + 85C, VCC = 4.75V to 7.0V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Characteristic Symbol Min Supply current Supply current (PLL powered down) Power down pin input logic high Power down pin input logic low Peak detector source current Peak detector leakage Data output Logic High Data output Logic Low Vih Vil Ipk IIK Voh Vol 0.7VCC 0.3VCC VCC-0.5 VEE-0.5 500 250 VCC+0.5 VEE+0.5 V V A nA V V IIoad = 10A lload = 10A ICC1 ICC2 Value Typ 2.30 1.90 Max 3.00 2.60 Units Conditions mA mA Vcc = 5V, all VCC = 5V, all Electrostatic discharge (ESD) protection (human body model) 2KV minimum, all pins. NOTES: Care must be taken not to power up the device with pins 7 and 8 shorted by a solder bridge, as operation with pin 7 grounded can damage the device and result in low sensitivity. ELECTRICAL CHARACTERISTICS A.C. Tamb = -40 to + 85C, VCC = 4.75V to 7.0V. These characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Characteristic Sensitivity See Note 1 Signal handling See Note 2 LNA input impedance Parallel combination R11/C11 Mixer input impedance Parallel combination R11/C11 Crystal oscillator input impedance Integrated IF filter -3dB low pass cut off frequency Spurious reverse isolation to RFIN See Note 3 Adjacent channel rejection See Note 4 Notes: 1. Sensitivity is defined as the minimum average signal level measured at the input necessary to achieve a bit error ratio of 10-2 where the input signal is a return to zero pulse (RZ) with an average duty cycle of 50%. The RF input is assumed to be matched into 50. Measured in test circuit Fig. 6 with data filter bandwidth of 5KHz as shown and for a 2Kbit/s, 50% duty cycle signal. 2. Signal handling is defined as the maximum input signal capable of being succcessfully de-modulated. It is assumed the input is ASK modulated with an extinction ratio of a least 40dB. The combination of this specification together with the sensitivity specification gives a minimum signal handling range of 76dB. The RF input is assumed to be matched into 50. Measured in test circuit Fig. 6. with data filter bandwidth of 5KHz as shown. 3. -67dBm in 50 measured with the RF input matching network. 4. Adjacent channel rejection is defined for an interfering tone (ACR) dB above threshold and 10MHz offset from the carrier giving a 3dB reduction in sensitivity i.e. the interfering tone is 4.74mV (rms) @ Fc 10MHz and to achieve the specified sensitivity the wanted signal will have to be increased to 2.2V (rms) 5. Please refer to Smith charts Fig.8 through to 10 covering frequency range 250-500MHz. Symbol Min -23.5 2.65//2.2 1.15//1.1 -0.77 IF3dB 450 Value Typ -103 Units Max -100 dBm dBm 3.61//2.2 1.21//1.62 K//pF K//pF K KHz V (rms) dB Conditions RS = 50, 434MHz, 2KB/s RS = 50, 434MHz, 2KB/s VCC = 5V; 25C ambient; 434MHz Also see note 5 VCC = 5V; 25C ambient; 434MHz Also see note 5 C5 = C4 = 18pF All RS = 500 10MHz offset from receiver VCO -1.8 550 100 -2.1 750 ACR 65 2 KESRX01 PIN LISTING Pin 1 2 3 4 5 6 7 8 9 10 11 12 Symbol IFDC1 IFDC2 IF1 IF2 VCC MIXIP RFOP VEERF RFIN DSN DATAOP PEAK Description IF amplifier - decouple point IF amplifer - decouple point Mixer output IF amplifer input Positive power supply RF mixer input (tank) RF amplifier output (tank) RF amplifier ground RF input (antenna) Bit slicer comparator negative input Bit slicer comparator output Peak detector output Pin 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VEE PD VCO1 VCO2 NC NC LF DF0 DF1 DF2 XTAL1 XTAL2 Description Negative power supply (0V) PLL power down VCO maintaining amplifer VCO maintaining amplifier Not connected, unless to GND Not connected,unless to GND PLL loop filter O/P output Data filter - external connection Data filter - external connection Data filter - external connection Crystal oscillator Crystal oscillator FUNCTION Phase locked loop The phase locked loop generates the local oscillator by frequency multiplication of a crystal referenced oscillator. Dividers A divide by 64 prescaler is present in the PLL feedback loop. The local oscillator frequency is then Fo=64xF ref . A system operating at 433.92MHz (RFIN) with a 270KHz IF frequency would require a reference of 6.77578MHz (assuming mixer low side injection). Alternative choice of crystal and tank components permit operation at specific frequencies in the range 290 - 460MHz. This phase detector has a triangle characteristic for an input phase error in the range -2 < <+2 and has the benefit of being a true frequency detector (as well as a phase detector) and hence will always achieve lock for any initial VCO frequency. The charge pump provides an output current in the range 30A and hence gives a phase detector gain of 4.8A/rad. The PLL loop characteristics such as lock-up time, capture range, loop bandwidth and VCO reference sideband suppression are controlled by the external loop filter. For the intended application a 2nd order loop should be sufficient as shown in the test circuit Fig. 6. Phase detector The phase detector used is a phase frequency detector (PFD) with a current (charge pump) output. VCO A balanced configuration is used with the LC tank connected externally across VCO1 and VCO2 Fig. 3. DP DPb VCO1 VCO2 Fig. 3 Input circuit of VCO and divider chain 3 KESRX01 External SAW resonator For reduced power the PLL based oscillator can be replaced by a SAW based oscillator. If pin PD is tied low (VEE) the crystal oscillator, dividers and phase detector/charge pump are powered down. The VCO can then be used as a maintaining amplifier for an external SAW based oscillator. The normal mode of operation is with PD set high (VCC) or alternatively left unconnected. Note: the power down facility is intended to be hard wired (either to VCC or VEE) and hence the PD pin is not specified for operation with normal CMOS or TTL logic levels. PD V CC /NC V EE MODE PLL Enable PLL Disable Down converting mixer The RF input is a.c. coupled into a doubly balanced mixer configuration. Its input impedance is given in Fig.8. IF filtering The IF filter has a (nominal) bandpass response from 25KHz to 550KHz. The single high pass section is provided by the combination of the external a.c. coupling capacitor between IF1 and IF2 and an on chip resistor (nominal value 12k). The low pass section is entirely on chip and to meet the selectivity requirements (adjacent channel rejection) this filter has 4 low pass poles with a Butterworth response. IF amplifiers and demodulator The majority of the receiver gain is provided in the form of an IF limiting strip. These amplifiers are all d.c. coupled and hence differential d.c. feedback is required. This is decoupled externally at pins IFDC1 and IFDC2. The IF amplifier stages also combine to provide a Received Signal Strength Indicator (RSSI) function. Since the modulation is ASK and the RSSI output has a linear output for a logarithmic change on its input then the RSSI output is the demodulated data. The only uncertainty is the d.c. level. Reference crystal oscillator A crystal stabilised oscillator provides a reference clock for the PLL. The oscillator is configured for parallel resonant operation in the fundamental mode (typical operating frequency of 4-7MHz). The crystal is connected between pins XTAL1, XTAL2 with external components as shown in Fig. 6. Note that this is a single transistor Colpitts oscillator where the external load capacitors must be taken into account in specifying the crystal. See Application Note AN207. Data filter Prior to the data slicer the demodulated data passes through a low pass filter. This filter is a 2nd order Sallen-Key section using an on chip voltage follower. External capacitors set the cutoff frequency and filter Q. The value of the on chipresistors is 100K (nominal). See Fig. 4. The cut-off frequency of the data filter,o, should be set to reduce high frequency noise into the data slicer without distorting the wanted signal. Normally this would be at least three times the data frequency. RF amplifier The RF amplifier consists of a low noise transistor in a common emitter configuration. A separate emitter connection is provided (VEERF) to reduce sensitivity to any common impedance in this path. The amplifier is current source biased so the signal (RFIN) should be a.c. coupled. The collector is open circuit so that the gain can be set with an external tuned load, Fig. 6. Its input impedance is given in Fig. 9 and output impedance in Fig. 10. C1 R DF0 R 100K CUT OFF FREQUENCY = fo DF1 DF2 C2 o = 2 . . fo . y C1 = 2.Q R . o C2 = 1 2 . Q . R o. BESSEL Q = 0.577 Y = 1.732 BUTTERWORTH Q = 0.71 Y = 1.0 Fig. 4 Choosing data filter components Example To implement a Bessel response filter with a 10KHz 3dB cutoff C1 = 106pF C2 = 80pF 4 KESRX01 Bit slicer and Peak Detector To provide maximum flexibility an independent data comparator is provided. External circuitry must be provided to obtain the bit slicer threshold level. Two basic approaches are supported. 1. For coding schemes with no d.c. content (e.g. Manchester coding or 33% / 66% pulse width encoding) this can be based on the integrated d.c. level (using a series R and C). See Application Note AN207. 2. For coding schemes with d.c. content (e.g. low duty cycle pulse width modulation) an active peak detector is included. The output at pin PEAK represents the peak level at the data filter output (as shown in Fig.5). An external RC time constant at this pin determines the maximum attack and decay times of the peak detector. Typical values for the leakage and diode current source capability are shown in the specifications. The comparator has relatively low drive capability (push/pull current source output of 20A) and hence DATOP should not be excessively loaded. On chip positive feedback around the comparator provides a nominal hysteresis level of 20mV. - + PEAK - + INTERNAL CIRCUIT PEAK LEVEL OUTPUT Fig. 5 Peak detector output Sensitivity In digital radio systems, sensitivity is often defined as the lowest signal level at the receiver input that will achieve a specified Bit Error Ratio (BER) at the output. The sensitivity of the KESRX01 receiver, when used in the 434MHz application shown in Fig. 6, is typically -103dBm average power (ASK modulated with 2kHz, 50% duty cycle square wave) to achieve a 0.01 BER. The input was matched for a 50 signal source. At 315MHz, -105dBm average power is typically achievable. Consult the Applications Notes refered to at the end of this Datasheet for detailed PCB design issues to secure perfomance. The local oscillator frequency is set at 433.65MHz with a required accuracy of at least 100kHz (see section below) i.e 433.55MHz to 433.75MHz. This guarantees that the IF (70KHz to 470KHz) falls within the acceptance bandwidth of the IF filter. The frequency of operation for such products in Europe is 433.05MHz to 434.79MHz. The choice of such a low IF frequency ensures that any image falls within the regulatory band. This in turn ensures that the receiver cannot be blocked by the image response of an unwanted signal outside of this band. Choice of IF frequency and IF bandwidth The IF frequency is selected to be nominally 270KHz with the low frequency cut-off at 25KHz and the high frequency cut-off at 550KHz (nominal). For worst case tolerances the transmitter frequency may be 433.92MHz 100KHz. i.e from 433.82MHz to 434.02MHz (see transmitter design specification application notes) Frequency Accuracy The stability of the local oscillator is equal to that of the crystal reference oscillator. Therefore to obtain a final output accuracy of 100KHz at 433MHz would require a crystal with a tolerance specification of 230ppm. This tolerance should encompass all causes e.g. initial accuracy, temperature stability and ageing. Choose a tighter tolerance crystal for increased frequency accuracy. 5 KESRX01 C17 C18 XTAL1 -15 V IF O/P IC1 RLY7 IF O/P SELECT 1 2 KESRX01 IFDC1 XTAL2 24 IFDC2 XTAL1 23 IF2 IF1 Vcc Mix IP DF2 DF1 DF0 22 21 20 C5 C4 DF2 O/P RSSI O/P Select RSSI O/P C8 +15 V R65 3 C9 Vcc 1 C16 4 5 6 7 8 C19 C20 RLY9 PLL SELECT Vcc 1 SELECT ATTENUATOR RF Input 0 dB 20 dB RLY 2 C14 C2 C1 L1 L2 C50 LF 19 RF OP Vee 2 18 Vee RF VARAC RF IN VCO2 17 16 15 NC NC L4 C11 C13 R8 VAR R9 13 VCO EXTERNAL VCO OVERDRIVE 9 10 DSN VCO1 11 Data O/P PD 14 12 Peak Vee 1 11 R55 C24 Data O/P Power Down R60 C12 R14 Fig. 6 KESRX01 Test circuit at 434MHz (peak detector slice mode) Component C1 C2 C4, C5 C8 C9 C11, C13 C12 C14 C16 C17, C18 C19 C20 C24 C50 R8 R9 R14 R55 R60 R65 L1 L2 L4 VAR XTAL Function Input Matching circuit Input Matching circuit XTAL feedback capacitors DC decoupling capacitor IF filter high pass VCO decouple PLL loop filter VCC decoupling capacitor RF amplifier load IF amplifier decouple Data filter Data filter Data slicer time constant VCC decoupling capacitor Varactor bias PLL loop filter Data slicer threshold circuit Data slicer threshold circuit Varactor bias IC1 bias RF amplifier input matching RF amplifier/Mixer matching network VCOtank circuit VCO tank circuit varactor Reference frequency Value 4.7 1 100 470 220 33 560 1 56 100 150 220 1 100 47 18 1 4.3 47 1 47 27 39 SMV-1104-35 6.775 Units pF pF pF pF pF pF pF F pF nF pF pF F pF K K M K K M nH nH nH 4 to 11pF MHz Table 1. Component values for test circuit 6 KESRX01 If required, the reference signal to the PLL can be driven externally from a stable signal source as shown in Fig. 7. Typically a 200mVp clock signal is ac coupled to produce differential output on OP and OPb. (C=10nF, Rs (source) < 5k) C CLK Rs XTAL2 XTAL1 OP OPb Fig. 7 Direct drive of crystal oscillator Applications For detailed applications support material consult the following Application Notes. AN207 AN4561 KESRX01 Demonstrator Receiver - A practical Application KESTX01/02 Demonstrator Transmitter 0.5 2.0 0 0.2 1 5 MIXER INPUT IMPEDANCE 250 TO 500MHz -0.5 -2.0 Fig. 8 KESRX01 mixer input impedance at -40, 27 and + 85 degrees 7 KESRX01 0.5 2.0 0. 0.2 1. 5. RF INPUT IMPEDANCE 250 TO 500MHz -0.5 -2.0 Fig. 9 KESRX01 LNA input impedance at -40, 27 and +85 degrees 0.5 2.0 0. 0.2 1 5 RF OUTPUT 250 TO 500MHz -0.5 -2.0 Fig. 10 KESSRX01 LNA output impedance at -40, 27 and +85 degrees 8 KESRX01 RF INPUT IMPEDANCE Min Freq MHz 303 315 403 418 434 0.935 0.935 0.935 0.934 0.934 -22.49 -23.43 -30.17 -31.29 -32.47 0.963 0.962 0.959 0.958 0.957 -23.16 -24.09 -30.74 -31.85 -33.02 0.975 0.999 0.999 0.969 0.968 -23.35 -24.26 -30.80 -31.89 -33.04 Mag Phase Mag Typ Phase Mag Max Phase RF OUTPUT IMPEDANCE Min Freq MHz 303 315 403 418 434 0.999 0.999 0.999 0.999 0.999 -14.62 -15.2 -19.37 -20.08 -20.83 0.999 0.999 0.999 0.999 0.999 -14.32 -14.88 -18.97 -19.67 -20.40 0.999 0.999 0.999 0.999 0.999 -13.92 -14.47 -19.36 -19.37 -19.84 Mag Phase Mag Typ Phase Mag Max Phase MIXER INPUT IMPEDANCE Min Freq MHz 303 315 403 418 434 0.927 0.926 0.925 0.925 0.925 -14.64 -15.16 -19.03 -19.98 -20.39 0.938 0.935 0.937 0.937 0.937 -14.42 -14.95 -18.82 -19.47 -20.17 0.949 0.949 0.948 0.948 0.948 -14.11 -14.63 -18.49 -19.11 -19.84 Mag Phase Mag Typ Phase Mag Max Phase 9 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. 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